LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;

ENTITY PFIO_tb IS
END PFIO_tb;

ARCHITECTURE PFIO_tb_arch OF PFIO_tb IS
    SIGNAL RST : STD_LOGIC;
    SIGNAL CLK : STD_LOGIC;
    SIGNAL RES : STD_LOGIC_VECTOR(7 DOWNTO 0);
    SIGNAL WC : STD_LOGIC_VECTOR(1 DOWNTO 0);
    SIGNAL WE : STD_LOGIC;
    SIGNAL F1 : STD_LOGIC_VECTOR(1 DOWNTO 0);
    SIGNAL F2 : STD_LOGIC_VECTOR(1 DOWNTO 0);
    SIGNAL C1 : STD_LOGIC_VECTOR(7 DOWNTO 0);
    SIGNAL C2 : STD_LOGIC_VECTOR(7 DOWNTO 0);

    COMPONENT PFIO IS
        PORT (
            -- RST signal
            RST : IN STD_LOGIC;
            -- CLOCK signal
            CLK : IN STD_LOGIC;
            -- INPUT RESULT for PF registers
            RES : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
            -- INPUT BITS for which register is written
            WC : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
            -- INPUT CONTROL BIT for written enable
            WE : IN STD_LOGIC;
            -- INPUT BITS for which register output result to C1
            F1 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
            -- INPUT BITS for which register output result to C2
            F2 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
            -- OUTPUT RESULT for result C1 out
            C1 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
            -- OUTPUT RESULT for result C2 out
            C2 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
        );
    END COMPONENT;

BEGIN
    U_PFIO : PFIO PORT MAP(
        RST => RST, CLK => CLK, RES => RES, WC => WC, WE => WE, F1 => F1, F2 => F2, C1 => C1, C2 => C2
    );

    PROCESS
    BEGIN
        RST <= '1';
        CLK <= '1';
        WAIT FOR 10 ns;
        CLK <= '0';
        RST <= '0';
        WAIT FOR 10 ns;
        CLK <= '1';
        WAIT FOR 10 ns;
        CLK <= '0';
        WAIT FOR 10 ns;
        CLK <= '1';
        WAIT FOR 10 ns;
        CLK <= '0';
        WAIT FOR 10 ns;
        CLK <= '1';
        WAIT FOR 10 ns;
        CLK <= '0';
        WAIT FOR 10 ns;
        CLK <= '1';
        WAIT FOR 10 ns;
        CLK <= '0';
        WAIT FOR 10 ns;
        CLK <= '1';
        WAIT FOR 10 ns;
        CLK <= '0';
        WAIT FOR 10 ns;
        CLK <= '1';
        WAIT FOR 10 ns;
        CLK <= '0';
        WAIT FOR 10 ns;
        CLK <= '1';
        WAIT FOR 10 ns;
        CLK <= '0';
        WAIT FOR 10 ns;
        CLK <= '1';
        WAIT FOR 10 ns;
        CLK <= '0';
        WAIT FOR 10 ns;
        CLK <= '1';
        WAIT FOR 10 ns;
        CLK <= '0';
        WAIT FOR 10 ns;
        CLK <= '1';
        WAIT FOR 10 ns;
        CLK <= '0';
        WAIT FOR 10 ns;
        CLK <= '1';
        WAIT FOR 10 ns;
        CLK <= '0';
        WAIT FOR 10 ns;
        CLK <= '1';
        WAIT FOR 10 ns;
        CLK <= '0';
        WAIT FOR 10 ns;
        CLK <= '1';
        WAIT FOR 10 ns;
        CLK <= '0';
        WAIT FOR 10 ns;
    END PROCESS;
END PFIO_tb_arch; -- PFIO_tb_arch